CMP-less ILD0 Planarization Technology for Gate-last Process

被引：0

作者：

Meng Lingkuan ^{[1
]}

Yin Huaxiang ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

来源：

CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2012 (CSTIC 2012) | 2012年 / 44卷 / 01期

关键词：

D O I：

10.1149/1.3694335

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

As CMOS technology scales to 32nm node and beyond, ILD0 planarization is one of critical technologies in high-K metal gate-last process integration. In this paper, a novel sub-micron gate-last process featuring with CMP-less spin-on glass/silicon oxide (SOG/SiO2) etch-back method was demonstrated for low cost logic platform. The innovative approach of SOG two steps plasma etch-back with O-2 treatment can be successfully used for ILD0 planarization of gate-last process. SEM results indicated that there was fairly little "dish effect" and step height close to zero on the 0.4 mu m gate-stack array and finally achieved a good planarization on the whole substrate.

引用

页码：331 / 335

页数：5

共 46 条

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