CMP-less ILD0 Planarization Technology for Gate-last Process

被引：0
|
作者：
Meng Lingkuan [1 ]
Yin Huaxiang [1 ]
机构：
[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China
来源：
CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2012 (CSTIC 2012) | 2012年 / 44卷 / 01期
关键词：
D O I：
10.1149/1.3694335
中图分类号：
O646 [电化学、电解、磁化学];
学科分类号：
081704 ;
摘要：
As CMOS technology scales to 32nm node and beyond, ILD0 planarization is one of critical technologies in high-K metal gate-last process integration. In this paper, a novel sub-micron gate-last process featuring with CMP-less spin-on glass/silicon oxide (SOG/SiO2) etch-back method was demonstrated for low cost logic platform. The innovative approach of SOG two steps plasma etch-back with O-2 treatment can be successfully used for ILD0 planarization of gate-last process. SEM results indicated that there was fairly little "dish effect" and step height close to zero on the 0.4 mu m gate-stack array and finally achieved a good planarization on the whole substrate.
引用
收藏
页码：331 / 335
页数：5
相关论文
共 46 条
  • [21] A Self-Aligned Gate-Last Process Applied to All-III-V CMOS on Si
    Jonsson, Adam
    Svensson, Johannes
    Wernersson, Lars-Erik
    IEEE ELECTRON DEVICE LETTERS, 2018, 39 (07) : 935 - 938
  • [22] High K Metal Gate CMP Process Development for 32nm & Beyond Gate Last Approach
    Shao, Qun
    Chen, Feng
    Jiang, Li
    Li, Mingqi
    Wang, Qingling
    Zhu, Pulei
    Cheng, Ji
    Xiong, Shiwei
    Liu, Hongtao
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2013 (CSTIC 2013), 2013, 52 (01): : 523 - 528
  • [23] Dual-Channel Technology with Cap-free Single Metal Gate for High Performance CMOS in Gate-First and Gate-Last Integration
    Witters, L.
    Mitard, J.
    Veloso, A.
    Hikavyy, A.
    Franco, J.
    Kauerauf, T.
    Cho, M.
    Schram, T.
    Sebai, F.
    Yamaguchi, S.
    Takeoka, S.
    Fukuda, M.
    Wang, W. -E.
    Duriez, B.
    Eneman, G.
    Loo, R.
    Kellens, K.
    Tielens, H.
    Favia, P.
    Rohr, E.
    Hellings, G.
    Bender, H.
    Roussel, P.
    Crabbe, Y.
    Brus, S.
    Mannaert, G.
    Kubicek, S.
    Devriendt, K.
    De Meyer, K.
    Ragnarsson, L. -A.
    Steegen, A.
    Horiguchi, N.
    2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
  • [24] Multideposition Multiroom-Temperature Annealing via Ultraviolet Ozone for HfZrO High-κ and Integration With a TiN Metal Gate in a Gate-Last Process
    Wu, Ling
    Yu, HongYu
    Yew, K. S.
    Pan, Jisheng
    Liu, W. J.
    Duan, Tian Li
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (07) : 2177 - 2181
  • [25] STUDY ON 28NM TECHNOLOGY NODE ILD0-CMP MICRO_SCRATCH DEFECT REDUCTION
    Ma, Xing
    Wang, Kailin
    Yu, Jianwen
    Que, Yurong
    Li, Hu
    Fang, Jingxun
    Zhang, Yu
    CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC, 2024,
  • [26] Characterization of number fluctuations in gate-last metal nanocrystal nonvolatile memory array beyond 90nm CMOS technology
    Lee, C
    Ganguly, U
    Kan, EC
    MATERIALS AND PROCESSES FOR NONVOLATILE MEMORIES, 2005, 830 : 223 - 228
  • [27] CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach
    Anil, KG
    Verheyen, P
    Collaert, N
    Dixit, A
    Kaczer, B
    Snow, J
    Vos, R
    Locorotondo, S
    Degroote, B
    Shi, X
    Rooyackers, R
    Mannaert, G
    Brus, S
    Yim, YS
    Lauwers, A
    Goodwin, M
    Kittl, JA
    van Dal, M
    Richard, O
    Veloso, A
    Kubicek, S
    Beckx, S
    Boullart, W
    De Meyer, K
    Absil, P
    Jurczak, M
    Biesemans, S
    2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2005, : 198 - 199
  • [28] Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process
    Zhang ShuXiang
    Yang Hong
    Tang Bo
    Tang Zhaoyun
    Xu Yefeng
    Xu Jing
    Yan Jiang
    JOURNAL OF SEMICONDUCTORS, 2014, 35 (10)
  • [29] Combining a multi deposition multi annealing technique with a scavenging(Ti) to improve the high-k/metal gate stack performance for a gate-last process
    张淑祥
    杨红
    唐波
    唐兆云
    徐烨峰
    许静
    闫江
    Journal of Semiconductors, 2014, 35 (10) : 186 - 190
  • [30] Integration Issue of Tensile SiN Liner for Dual Stress Liner(DSL) in Gate-Last High-k/Metal Gate( HKMG) Process Flow
    Qin, Changliang
    Yin, Haizhou
    Yin, Huaxiang
    Wang, Guilei
    Hong, Peizhen
    Yang, Tao
    Lu, Yihong
    Xu, Qiang
    Zhao, Zhiguo
    Cui, Hushan
    Zhao, Chao
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2013 (CSTIC 2013), 2013, 52 (01): : 677 - 681
12345