The challenges of sub-20nm shallow trench isolation etching

被引：0

作者：

Zhou, Hui ^{[1
]}

Ji, Xiaosong ^{[1
]}

Srinivasan, Sunil ^{[1
]}

He, Jim ^{[1
]}

Hua, Xuefeng ^{[1
]}

Agarwal, Ankur ^{[1
]}

Rauf, Shahid ^{[1
]}

Todorow, Valentin N. ^{[1
]}

Choi, Jinhan ^{[1
]}

Khan, Anisul ^{[1
]}

机构：

[1] Appl Mat Inc, Santa Clara, CA 95054 USA

来源：

SOLID STATE TECHNOLOGY | 2013年 / 56卷 / 04期

关键词：

PATTERN COLLAPSE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Major challenges for sub-20nm STI etching include intra-cell depth loading, across-wafer uniformity, etch profile control near the wafer edge, and propensity for pattern collapse.

引用

页码：14 / 18

页数：5

共 50 条

[1] Materials Challenges for sub-20nm lithography
Thackeray, James W.
ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXVIII, 2011, 7972
[2] Develop Gap-fill Process of Shallow Trench Isolation in 450mm Wafer by Advanced Flowable CVD Technology for Sub-20nm Node
Chen, Min-Hui
Chang, Stock
2016 27TH ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC), 2016, : 157 - 159
[3] Middle of Line (MoL) Cleaning Challenges in Sub-20nm Node Device Manufacturing
Singh, SherJang
Muralidhar, Pranesh
Mallabar, Samuel
Scott, Silas
ULTRA CLEAN PROCESSING OF SEMICONDUCTOR SURFACES XIII, 2016, 255 : 105 - 110
[4] Choices and challenges for shallow trench isolation
Peters, Laura
Semiconductor International, 1999, 22 (04):
[5] Laser Spike Annealing Resolves Sub-20nm Logic Device Manufacturing Challenges
Wang, Yun
SOLID STATE TECHNOLOGY, 2014, 57 (08) : 16 - 20
[6] Fracture of Sub-20nm Ultrathin Gold Nanowires
Lu, Yang
Song, Jun
Huang, Jian Yu
Lou, Jun
ADVANCED FUNCTIONAL MATERIALS, 2011, 21 (20) : 3982 - 3989
[7] Fabricating vertically aligned sub-20nm Si nanowire arrays by chemical etching and thermal oxidation
Li, Luping
Fang, Yin
Xu, Cheng
Zhao, Yang
Zang, Nanzhi
Jiang, Peng
Ziegler, Kirk J.
NANOTECHNOLOGY, 2016, 27 (16)
[8] EUV mask inspection study for sub-20nm device
Shin, Inkyun
Yoon, Gisung
Na, Ji Hoon
Chung, Paul D. H.
Jeon, Chanuk
PHOTOMASK TECHNOLOGY 2012, 2012, 8522
[9] Investigation of Sub-20nm 4th generation DRAM cell transistor's parasitic resistance and scalable methodology for Sub-20nm era
Jeong, Shinwoo
Lee, Jin-Seong
Jang, Jiuk
Kim, Jooncheol
Shin, Hyunsu
Kim, Ji Hun
Song, Jeongwoo
Woo, Dongsoo
Oh, Jeonghoon
Lee, Jooyoung
2023 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS, 2023,
[10] A Novel technique for the fabrication of sub-20nm metallic wires
Hoole, ACF
Broers, AN
MICROELECTRONIC ENGINEERING, 1996, 30 (1-4) : 467 - 470

← 1 2 3 4 5 →