共 50 条
- [42] Novel DPT methodology co-optimized with Design Rules for sub-20nm device PHOTOMASK TECHNOLOGY 2012, 2012, 8522
- [43] A novel sub-20nm Depletion-Mode Double-Gate (DMDG) FET 2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2003, : 243 - 246
- [44] An improved method for characterizing photoresist lithographic and defectivity performance for sub-20nm node lithography ADVANCES IN PATTERNING MATERIALS AND PROCESSES XXXIII, 2016, 9779
- [45] Improvement of sub-20nm pattern quality with dose modulation technique for NIL template production ALTERNATIVE LITHOGRAPHIC TECHNOLOGIES VIII, 2016, 9777
- [46] Novel Hardmask For sub-20nm Copper/Low k Backend Dual Damascene Integration SILICON NITRIDE, SILICON DIOXIDE, AND EMERGING DIELECTRICS 11, 2011, 35 (04): : 651 - 665
- [48] Direct measurement of effects of shallow-trench isolation on carrier profiles in sub-50 nm N-MOSFETs 2005 Symposium on VLSI Technology, Digest of Technical Papers, 2005, : 140 - 141
- [50] An optimized shallow trench isolation for sub-0.18um ASIC technologies MICROELECTRONIC DEVICE TECHNOLOGY II, 1998, 3506 : 156 - 166