Design and Analysis of 6T, 8T and 9T Decanano SRAM Cell at 45 nm Technology

Data retention and leakage current reduction are among the major area of concern in today's CMOS technology. In this paper 6T, 8T and 9T SRAM cell have been compared on the basis of read noise margin (RNM), write noise margin (WNM), read delay, write delay, data retention voltage (DRV), layout and parasitic capacitance. Corner and statistical simulation of the noise margin has been carried out to analyze the effect of intrinsic parameter fluctuations. Both 81 SRAM cell and 9T SRAM cell provides higher read noise margin (around 4 times increase in RNM) as compared to 61 SRAM cell. Although the size of 8T SRAM cell is around 1.35 times higher than that of the 81 SRAM cell but it provides higher write stability. Due to single ended bit line sensing the write stability of 8T SRAM cell is greatly affected. The 8T SRAM cell provides a write "1" noise margin which is approximately 3 times smaller than that of the 9T SRAM cell. The data retention voltage for 8T SRAM cell was found to be 93.64 mV while for 91 SRAM cell it was 84.5 mV and for 6T SRAM cell it was 252.3 mV. Read delay for 9T SRAM cell is 98.85 ps while for 6T SRAM cell it is 72.82 ps and for 8T SRAM cell it is 77.72 ps. The higher read delay for 9T SRAM cell is attributed to the fact that dual threshold voltage technology has been in it in order to reduce the leakage current. Write delay for 9T SRAM cell was found to be 10 ps, 45.47 ps for 81 SRAM cell and 8.97 ps for 6T SRAM cell. The simulation has been carried out on 45 nm CMOS technology.