A Low Cost Robust Radiation Hardened Flip-Flop Circuit

被引：0

作者：

Jain, A. ^{[1
]}

Gupta, A. ^{[1
]}

Garg, S. ^{[1
]}

Veggetti, A. ^{[2
]}

Castelnovo, A. ^{[2
]}

Crippa, D. ^{[2
]}

Gerardin, S. ^{[3
]}

Bagatin, M. ^{[3
]}

Cazzaniga, C. ^{[4
]}

机构：

[1] STMicroelectronics Pvt Ltd, Greater Noida, India

[2] STMicroelectronics Srl, Agrate Brianza, Italy

[3] Univ Padua, Padua, Italy

[4] Rutherford Appleton Lab, Didcot, Oxon, England

来源：

TENCON 2017 - 2017 IEEE REGION 10 CONFERENCE | 2017年

关键词：

Soft error; single-event upset; single-event; Flip-flop; sequential logic circuits; SOFT ERRORS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new radiation hardened flip-flop, named low power single-phase clocked rad-hard flip flop, is proposed. The structure is based on robust differential-input latches working on a single-phase clock, which allows a reduction in the number of nodes sensitive to radiation. The proposed structure optimizes area and power and offers better performance, as compared to state-of-the-art techniques. Experimental results from test chip manufactured in a 180-nm BCD technology exposed to heavy ions, neutrons and alpha particles show that the proposed structure significantly reduces single event upsets (SEU).

引用

页码：494 / 499

页数：6

共 50 条

[31] Robust Flip-Flop Circuit against Soft Errors for Combinational and Sequential Logic Circuits
Uemura, Taiki
Tosaka, Yoshiharu
Matsuyama, Hideya
Takahisa, Keiji
Fukuda, Mitsuhiro
Hatanaka, Kichiji
JAPANESE JOURNAL OF APPLIED PHYSICS, 2009, 48 (04)
[32] Robust flip-flop circuit against soft errors for combinational and sequential logic circuits
Fujitsu Microelectronics Ltd., 1500 Mizono, Tado, Kuwana, Mie 511-0192, Japan
不详
Jpn. J. Appl. Phys., 1600, 4 PART 2
[33] Design of arbitrary value flip-flop circuit and register
Chen, Shu-Kai
Lin, Gang
Changsha Dianli Xueyuan Xuebao/Journal of Changsha University of Electric Power, 2002, 17 (03):
[34] Switched flip-flop based preprocessing circuit for ISFETs
Kollár, M
SENSORS, 2005, 5 (03): : 118 - 125
[35] A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop
Islam, Riadul
2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2012, : 347 - 352
[36] Area-Efficient Temporally Hardened by Design Flip-Flop Circuits
Matush, Bradley I.
Mozdzen, Thomas John
Clark, Lawrence T.
Knudsen, Jonathan E.
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2010, 57 (06) : 3588 - 3595
[37] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process
Yamaguchi, Junki
Furuta, Jun
Kobayashi, Kazutoshi
2015 15TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS (RADECS), 2015,
[38] A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process
Furuta, Jun
Yamaguchi, Junki
Kobayashi, Kazutoshi
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2016, 63 (04) : 2080 - 2086
[39] A low clock load conditional flip-flop
Hansson, M
Alvandpour, A
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2004, : 169 - 170
[40] Flip-flop flap
Reebs, Stephan
NATURAL HISTORY, 2007, 116 (07) : 12 - 12

← 1 2 3 4 5 →