Low Complexity Deblocking Algorithm and Implementation with a Configurable Processor

A low complexity algorithm for post-processing deblocking and Implementation with a configurable processor designed by us is presented In this paper. The algorithm is aimed at Improving subjective visual effect and reducing the complexity for hardware design. According to the masking effect of human visual system (HVS), the blocking artifacts can be recognized only when the blocking artifacts continually appear on the boundaries of the blocks. Based on this, we proposed a novel algorithm that the deblocking will be processed only on the region which has simple image and mass blocking artifacts. Undesirable blue can be prevented. The hardware implementation with a configurable processor Improves flexibility in application for different video compression standards and shorts the time-to-market. Our configurable processor is based on Transport Triggered Architecture (TTA). The design in RTL Is synthesized using 0.18um TSMC library. The simulation result shows that the proposed algorithm can earn better visual effect and hardware architecture can meet the real-time deblocking processing for CIF format video sequence at a system clock of 70MHz.