Demonstration of scaled Ge p-channel FinFETs integrated on Si

被引：0

作者：

van Dal, M. J. H. ^{[1
]}

Vellianitis, G. ^{[1
]}

Doornbos, G. ^{[1
]}

Duriez, B. ^{[1
]}

Shen, T. M. ^{[2
]}

Wu, C. C. ^{[2
]}

Oxland, R. ^{[1
]}

Bhuwalka, K. ^{[1
]}

Holland, M. ^{[1
]}

Lee, T. L. ^{[2
]}

Wann, C. ^{[2
]}

Hsieh, C. H. ^{[3
]}

Lee, B. H. ^{[3
]}

Yin, K. M. ^{[3
]}

Wu, Z. Q. ^{[2
]}

Passlack, M. ^{[1
]}

Diaz, C. H. ^{[2
]}

机构：

[1] TSMC R&D, Kapeldreef 75, B-3001 Leuven, Belgium

[2] TSMC R&D, Hsinchu 30844, Taiwan

[3] TSMC QRA, Hsinchu 30077, Taiwan

来源：

2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2012年

关键词：

FIELD; PERFORMANCE; TEMPERATURE; PMOSFETS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/mu m at 1V, 1.05 mS/mu m at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest g(m)/SS at V-dd=1V reported for non-planar unstrained Ge pFETs to date.

引用

页数：4

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