Test Compaction Techniques for Assertion-Based Test Generation

被引：7

作者：

Tong, Jason G. ^{[1
]}

Boule, Marc ^{[2
]}

Zilic, Zeljko ^{[1
]}

机构：

[1] McGill Univ, Integrated Microsyst Lab, Montreal, PQ, Canada

[2] Ecole Technol Super, Montreal, PQ, Canada

来源：

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | 2013年 / 19卷 / 01期

关键词：

Verification; Design; SVA; assertion-based verification; functional validation; directed test generation; test compaction; COVERAGE;

D O I：

10.1145/2534397

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Assertions are now widely used in verification as a means to help convey designer intent and also to simplify the detection of erroneous conditions by the firing of assertions. With this expressive modeling power, assertions could also be used for tasks such as helping to assess test coverage and even as a source for test generation. Our work deals with this last aspect, namely, assertion-based test generation. In this article, we present our compacted test generation scheme based on assertions. Novel compaction techniques are presented based on assertion clustering, test-path overlap detection and parallel-path removal. Our compaction approach is experimentally evaluated using nearly 300 assertions to show the amount of reduction that can be obtained in the size of the test sets. This ultimately has a positive impact on verification time in the quest for bugfree designs.

引用

页数：29

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