Applied Assertion-Based Verification: An Industry Perspective

A wealth of material has been published over the past 30 years specifically related to the theory and technical aspects of property languages and assertion-based techniques. However, as any field of study matures, it becomes necessary to determine if the theories, algorithms, and concepts have grown beyond the bounds of research to become an integral solution to a problem in industry. To understand any solution, it is necessary to understand the problem. For example, debugging, on average, has grown to consume more than 60% of today's ASIC and SoC verification effort. Clearly, this is a topic the industry must address, and some organizations have done just that. Those that have adopted an assertion-based verification (ABV) methodology have seen a significant reduction in simulation debugging time (as much as 50% [1, 47]) due to improved observability. Furthermore, organizations that have embraced an ABV methodology are able to take advantage of more advanced verification techniques, such as formal property checking, thus improving their overall verification quality and results. This paper examines the application of ABV in today's electronic design industry to address specific challenges of poor observability and controllability during the verification process. Statistics illustrating successful application of both low-level and high-level assertions are presented. While the process of writing assertions is fairly well understood by those skilled in the art the process of creating higher-level assertion-based IP that must communicate with other components in a contemporary transaction-level modeling (TLM) simulation environment, is not. Hence, this paper provides a set of steps (in a tutorial fashion) for creating assertion-based IP.