Resonant Body Transistors in IBM's 32nm SOI CMOS Technology

被引：0
|
作者：
Marathe, R. [1 ]
Wang, W. [1 ]
Mahmood, Z. [1 ]
Daniel, L. [1 ]
Weinstein, D. [1 ]
机构：
[1] MIT, Cambridge, MA 02139 USA
来源：
IEEE INTERNATIONAL SOI CONFERENCE | 2012年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页数：2
相关论文
共 50 条
  • [41] Overview and Future Challenges of Floating Body RAM (FBRAM) Technology for 32nm Technology Node and Beyond
    Hamamoto, Takeshi
    Ohsawa, Takashi
    ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2008, : 25 - 29
  • [42] A 210GHz Fully Integrated Differential Transceiver with Fundamental-Frequency VCO in 32nm SOI CMOS
    Wang, Zheng
    Chiang, Pei-Yuan
    Nazari, Peyman
    Wang, Chun-Cheng
    Chen, Zhiming
    Heydari, Payam
    2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 136 - +
  • [43] Performance comparison of static CMOS and MCML gates in sub-threshold region of operation for 32nm CMOS technology
    Agarwal, Tarun Kumar
    Sawhney, Anurag
    Kureshi, A. K.
    Hasan, Mohd
    2008 INTERNATIONAL CONFERENCE ON COMPUTER AND COMMUNICATION ENGINEERING, VOLS 1-3, 2008, : 284 - 287
  • [44] An Ultra-High Bandwidth Sub-Ranging ADC with Programmable Dynamic Range in 32nm CMOS SOI
    Hsueh, Jen-Chieh
    Chen, Vanessa
    Plouchart, Jean-Oliver
    2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2017, : 448 - 451
  • [45] Total Ionizing Dose Characterization of a Custom Front-End SoC for Antenna Arrays in 32nm SOI CMOS
    Zanchi, Alfio
    Cabanas-Holmen, Manuel
    Amort, Anthony
    Brees, Roger
    2018 IEEE RADIATION EFFECTS DATA WORKSHOP (REDW), 2018, : 283 - 289
  • [46] Challenges of implementing contour modeling in 32nm technology
    Fischer, Daniel
    Han, Geng
    Oberschmidt, James
    Cheng, Yong Wah
    Maeng, Jae Yeol
    Archie, Charles
    Lu, Wei
    Tabery, Cyrus
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXII, PTS 1 AND 2, 2008, 6922 (1-2):
  • [47] Contact Patterning Strategies for 32nm and 28nm Technology
    Morgenfeld, Bradley
    Stobert, Ian
    An, Ju J.
    Kanai, Hideki
    Chen, Norman
    Aminpur, Massud
    Brodsky, Colin
    Thomas, Alan
    OPTICAL MICROLITHOGRAPHY XXIV, 2011, 7973
  • [48] Designing of Schmitt Trigger Based on Current Sink Logic Using 32NM CMOS and CNFET Technology
    Saxena, Namrata
    Agarwal, Rishabh
    Bairathi, Rakesh
    Periasamy, C.
    2016 INTERNATIONAL CONFERENCE ON RECENT ADVANCES AND INNOVATIONS IN ENGINEERING (ICRAIE), 2016,
  • [49] An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond
    Shao, I.
    Cotte, J. M.
    Haran, B.
    Topol, A. W.
    Simonyi, E. E.
    Cabral, C., Jr.
    Deligianni, H.
    PROCEEDINGS OF THE IEEE 2007 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2007, : 102 - 104
  • [50] Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology
    Huang Z.-F.
    Pan S.-J.
    Cao J.-F.
    Song T.
    Ouyang Y.-M.
    Liang H.-G.
    Ni T.-M.
    Lu Y.-C.
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2021, 49 (02): : 394 - 400
12345