Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node

被引：0
|
作者：
Suthram, S. [1 ]
Sun, Y.
Majhi, P. [3 ]
Ok, I. [2 ,5 ]
Kim, H. [2 ,5 ]
Harris, H. R.
Goel, N.
Parthasarathy, S. [7 ]
Koehler, A. [7 ]
Acosta, T. [7 ]
Nishida, T. [7 ]
Tseng, H. -H.
Tsai, W. [6 ]
Lee, J. [2 ,5 ]
Jammy, R. [4 ]
Thompson, S. E. [7 ]
机构：
[1] Intern Univ Florida, Gainesville, FL 32611 USA
[2] SEMATECH, Austin, TX USA
[3] Intel Assignee, Austin, TX USA
[4] IBM Corp, Armonk, NY USA
[5] Univ Texas Austin, Austin, TX 78712 USA
[6] Intel Corp, Santa Clara, CA USA
[7] Univ Florida, Gainesville, FL USA
来源：
2008 SYMPOSIUM ON VLSI TECHNOLOGY | 2008年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：143 / +
页数：2
相关论文
共 50 条
  • [21] Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node
    Kang, C. Y.
    Baek, R-H.
    Kim, T-W
    Ko, D.
    Kim, D-H.
    Michalak, T.
    Borst, C.
    Veksler, D.
    Bersuker, G.
    Hill, R.
    Hobbs, C.
    Kirsch, P. D.
    2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
  • [22] Advanced multi-patterning using resist core spacer process for 22nm node and beyond
    Kuwahara, Yuhei
    Shimura, Satoru
    Kyouda, Hideharu
    Oyama, Kenichi
    Yamauchi, Shohei
    Hara, Arisa
    Natori, Sakurako
    Yaegashi, Hidetami
    ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXIX, 2012, 8325
  • [23] Assessment of III-V FinFETs at 20 nm node: A Process variation analysis
    Pradhan, K. P.
    Singh, D.
    Mohapatra, S. K.
    Sahu, P. K.
    3RD INTERNATIONAL CONFERENCE ON RECENT TRENDS IN COMPUTING 2015 (ICRTC-2015), 2015, 57 : 454 - 459
  • [24] High etching selectivity of spin-on-carbon hard mask process for 22nm node and beyond
    Iwao, Fumiko
    Shimura, Satoru
    Kyouda, Hideharu
    Oyama, Kenichi
    Yamauchi, Shohei
    Hara, Arisa
    Natori, Sakurako
    Yaegashi, Hidetami
    ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXIX, 2012, 8325
  • [25] Advances on III-V MOSFET for Science and Technology beyond Si CMOS
    Kwo, J.
    Lin, T. D.
    Huang, M. L.
    Chang, P.
    Lee, Y. J.
    Hong, M.
    SILICON NITRIDE, SILICON DIOXIDE, AND EMERGING DIELECTRICS 10, 2009, 19 (02): : 593 - +
  • [26] Issues on Interfacial Oxide Layer (IL) in EOT Scaling of High-k/Metal Gate CMOS for 22nm Technology Node and Beyond
    Park, C. S.
    Kirsch, P. D.
    PHYSICS AND TECHNOLOGY OF HIGH-K MATERIALS 8, 2010, 33 (03): : 45 - 52
  • [27] Transmission line Model for inherently stable MSWCNT bundled global interconnect for 22nm Technology Node
    Mishra, Shailendra
    Mishra, Divya
    2017 4TH IEEE UTTAR PRADESH SECTION INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND ELECTRONICS (UPCON), 2017, : 184 - 190
  • [28] Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond
    Baklanov, Mikhail R.
    Smirnov, Evgeny A.
    Zhao, Larry
    SILICON NITRIDE, SILICON DIOXIDE, AND EMERGING DIELECTRICS 11, 2011, 35 (04): : 717 - 728
  • [29] Double patterning combined with shrink technique to extend ArF lithography for contact holes to 22nm node and beyond
    Miao, Xiangqun
    Huli, Lior
    Chen, Hao
    Xu, Xumou
    Wo, Hyungje
    Bencher, Chris
    Shu, Jen
    Ngai, Chris
    Borst, Christopher
    OPTICAL MICROLITHOGRAPHY XXI, PTS 1-3, 2008, 6924
  • [30] UV-NIL template for the 22nm node and beyond - art. no. 67305P
    Hiraka, Takaaki
    Yusa, Satoshi
    Fujii, Akiko
    Sasaki, Shiho
    Itoh, Kimio
    Toyama, Nobuhito
    Kurihara, Masaaki
    Mohri, Hiroshi
    Hayashi, Naoya
    PHOTOMASK TECHNOLOGY 2007, PTS 1-3, 2007, 6730 : P7305 - P7305
12345