Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications

This paper proposes a 2-D analytical model developed for Double Gate Junctionless Transistor with a SiO2/HfO(2)stacked oxide structure. The model is solved by Poisson's equation using the variable separation method. The proposed model gives analytical expressions for electrostatic potential distribution, threshold voltage and drain current with the effects of depletion regions at source/drain side. Furthermore, the potential and drain current models are used to evaluate the Short Channel Effects (SCEs) of the proposed device. The electrical characteristics and SCEs are analyzed by different possible definitions of channel length, silicon thickness, equivalent oxide thickness, and depletion length variations. The developed model results are validated through comparison with Sentarus TCAD simulator results. In addition, the proposed device is also studied for the digital circuit performance of CMOS inverter circuit by the voltage transfer characteristics, transient analysis, and AC small signal analysis.