A low-power implementation of asynchronous 8051 employing adaptive pipeline structure

被引：10

作者：

Lee, Je-Hoon ^{[1
]}

Kim, Young Hwan ^{[2
]}

Cho, Kyoung-Rok ^{[1
]}

机构：

[1] Chungbuk Natl Univ, BK Chungbuk Informat Technol Ctr 21, Chungbuk 361763, South Korea

[2] Pohang Univ Sci & Technol, Dept Elect Engn, Pohang 790784, South Korea

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2008年 / 55卷 / 07期

关键词：

asynchronous logic circuits; computer architecture; microprocessor; pipelines; power analysis;

D O I：

10.1109/TCSII.2008.921589

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a low-power implementation of the A8051 processor. It employs an adaptive pipeline structure that allows to skip a redundant stage operation and to combine with the neighboring empty stage. The processor has three features to reduce the power dissipation as well as to improve performance: multilooping control for multicycle instructions, branch predictor for unconditional branches, and a single threading in the EXE stage. The experimental results show that A8051 runs about 1.8 times faster than the synchronous counterpart, CIP51 [reported in the HC8051F0xx Family Datasheet (2002)]. In terms of Et-2, our implementation shows 15 times higher efficiency than that of asynchronous counterpart developed by the Nanyang University [Chang and Gwee (2006)].

引用

页码：673 / 677

页数：5

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