Performance Evaluation of Reliability Aware Photonic Network-on-Chip Architectures

被引:0
|
作者
Kaliraj, Pradheep Khanna [1 ]
Sieber, Patrick [1 ]
Ganguly, Amlan [1 ]
Datta, Ipshita [2 ]
Datta, Debasish [2 ]
机构
[1] Rochester Inst Technol, Dept Comp Engn, Rochester, NY 14623 USA
[2] Indian Inst Technol, Dept Elect & Elect Commun Engn, Kharagpur, W Bengal, India
来源
2012 INTERNATIONAL GREEN COMPUTING CONFERENCE (IGCC) | 2012年
关键词
Network-on-Chip; photonic interconnects; performance evaluation;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Network-on-Chip (NoC) is the preferred communication backbone for modern multicore chips. However, the multi-hop data transmission using wireline interconnects result in high energy dissipation and latency. Photonic interconnects have emerged as a promising alternative to the conventional metal/dielectric based on-chip wireline interconnects. Several novel architectures have been proposed using photonic waveguides as interconnects, which are capable of reducing the energy dissipation in data transfer significantly. However, the issues of reliability arising due to waveguide losses and adjacent channel crosstalk in photonic waveguides have not received much attention till date. In this paper we evaluate the performance of a photonic NoC architecture designed by segmenting the waveguides into smaller parts to limit the waveguide losses. This multi-segmented bus based photonic NoC (MSB-PNoC) architecture has been shown to provide higher levels of reliability than state-of-the-art photonic NoCs. Through detailed system level simulations in this work we demonstrate that the MSB-PNoC has a better performance and lower energy dissipation compared to the conventional mesh NoC while also providing better reliability in data transfer than other photonic NoCs.
引用
收藏
页数:6
相关论文
共 50 条
  • [31] Network-on-chip architectures and design methodologies
    Palesi, Maurizio
    Kumar, Shashi
    Marculescu, Radu
    MICROPROCESSORS AND MICROSYSTEMS, 2011, 35 (02) : 83 - 84
  • [32] Performance and Energy Evaluation of Network-On-Chip Infrastructure
    Kiran
    Solanki, Kamna
    2016 INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTATION TECHNOLOGIES (ICICT), VOL 3, 2015, : 848 - 852
  • [33] Machine learning-driven performance assessment of network-on-chip architectures
    Patra, Ramapati
    Maji, Prasenjit
    Srivastava, Dipti Sakshi
    Mondal, Hemanta Kumar
    JOURNAL OF SUPERCOMPUTING, 2024, 80 (16): : 24483 - 24519
  • [34] Performance and Power Optimization through Data Compression in Network-on-Chip Architectures
    Das, Reetuparna
    Mishra, Asit K.
    Nicopoulos, Chrysostomos
    Park, Dongkook
    Narayanan, Vijaykrishnan
    Iyer, Ravishankar
    Yousif, Mazin S.
    Das, Chita R.
    2008 IEEE 14TH INTERNATIONAL SYMPOSIUM ON HIGH PEFORMANCE COMPUTER ARCHITECTURE, 2008, : 198 - +
  • [35] Power and performance analysis of 3D network-on-chip architectures
    Halavar, Bheemappa
    Talawar, Basavaraj
    COMPUTERS & ELECTRICAL ENGINEERING, 2020, 83
  • [36] Design Trade off and Performance Analysis of Router Architectures in Network-on-Chip
    Latif, Jawwad
    Chaudhry, Hassan Nazeer
    Azam, Sadia
    Baloch, Naveed Khan
    10TH INTERNATIONAL CONFERENCE ON FUTURE NETWORKS AND COMMUNICATIONS (FNC 2015) / THE 12TH INTERNATIONAL CONFERENCE ON MOBILE SYSTEMS AND PERVASIVE COMPUTING (MOBISPC 2015) AFFILIATED WORKSHOPS, 2015, 56 : 421 - 426
  • [37] On Improving the Performance of Hybrid Wired-Wireless Network-on-Chip Architectures
    Zong, Wen
    Agyeman, Michael Opoku
    NINTH INTERNATIONAL WORKSHOP ON NETWORK ON CHIP ARCHITECTURES, NOCARC 2016, 2016, : 27 - 32
  • [38] High-Performance Adaption of ARM Processors into Network-on-Chip Architectures
    Tung Nguyen
    Duy-Hieu Bui
    Hai-Phong Phan
    Trang-Trinh Dang
    Xuan-Tu Tran
    2013 IEEE 26TH INTERNATIONAL SOC CONFERENCE (SOCC), 2013, : 222 - 227
  • [39] Power-Aware Mapping for Network-on-Chip Architectures under Bandwidth and Latency Constraints
    Wang, Xiaohang
    Yang, Mei
    Jiang, Yingtao
    Liu, Peng
    PROCEEDINGS OF THE 2009 FOURTH INTERNATIONAL CONFERENCE ON EMBEDDED AND MULTIMEDIA COMPUTING, 2009, : 91 - +
  • [40] Cache-aware network-on-chip for chip multiprocessors
    Tatas, Konstantinos
    Kyriacou, Costas
    Dekoulis, George
    Demetriou, Demetris
    Avraam, Costas
    Christou, Anastasia
    VLSI CIRCUITS AND SYSTEMS IV, 2009, 7363