A 0.87 mW 7MHz-BW 76dB-SNDR Passive Noise-Shaping Modulator Based On A SAR ADC

The successive approximation register (SAR) ADC plays a key role in moderate resolution and conversion rate. In higher resolution occasion, pipeline ADC is a better choice but it needs higher power consumption. SAR ADC with a passive noise-shaping modulator is an appropriate choice to increase the ENOB and save power consumption. This paper proposes a design of a 3rd order passive noise-shaping modulator based on a SAR ADC in 65 nm CMOS technology, The simulation result realizes 76 dB SNDR at 80MS/s sampling frequency. It only consumes 0.87mW and achieves a FoMw of 11.9fJ/conv. step and FoMs of 175.22dB.