Leakage Characterization of 10T SRAM Cell

被引：106

作者：

Islam, A. ^{[1
]}

Hasan, M. ^{[2
]}

机构：

[1] Birla Inst Technol, Dept Elect & Commun Engn, Ranchi 835215, Jharkhand, India

[2] Aligarh Muslim Univ, Dept Elect Engn, Aligarh 202002, Uttar Pradesh, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2012年 / 59卷 / 03期

关键词：

Read static noise margin (RSNM); SRAM; standby power; variability; POWER APPLICATIONS; HIGH-SPEED; CMOS; VARIABILITY; DESIGN;

D O I：

10.1109/TED.2011.2181387

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a technique for designing a low-power and variability-aware SRAM cell. The cell achieves low power dissipation due to its series-connected tail transistor and read buffers, which offer a stacking effect. This paper studies the impact of process, voltage, and temperature (PVT) variations on most of the design metrics of the SRAM cell and compares the results with standard 6T, 9T, and ST10T (Schmitt trigger based) SRAM cells.

引用

页码：631 / 638

页数：8

共 50 条

[31] 10T SRAM Design By Using Stack Transistor Technique
Mapari, Sneha K.
Sharma, Manish
2018 FOURTH INTERNATIONAL CONFERENCE ON COMPUTING COMMUNICATION CONTROL AND AUTOMATION (ICCUBEA), 2018,
[32] Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell
Kumar, C. I.
Anand, B.
ELECTRONICS LETTERS, 2018, 54 (25) : 1423 - 1424
[33] Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications
Shekhar, Raghav
Kumar, Chaudhry Indra
INTEGRATION-THE VLSI JOURNAL, 2022, 87 : 176 - 181
[34] Single-Ended 10T SRAM Cell with High Yield and Low Standby Power
Shakouri, Erfan
Ebrahimi, Behzad
Eslami, Nima
Chahardori, Mohammad
CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2021, 40 (07) : 3479 - 3499
[35] A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability
Jahinuzzaman, Shah M.
Rennie, David J.
Sachdev, Manoj
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, 56 (06) : 3768 - 3773
[36] SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects
Sudha, D.
Rani, Ch. Santhi
Ijjada, Sreenivasa Rao
ACTA PHYSICA POLONICA A, 2019, 135 (04) : 702 - 704
[37] Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability
Kumar, Manoj R.
Sridevi, P., V
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2021, 30 (08)
[38] Single-Ended 10T SRAM Cell with High Yield and Low Standby Power
Erfan Shakouri
Behzad Ebrahimi
Nima Eslami
Mohammad Chahardori
Circuits, Systems, and Signal Processing, 2021, 40 : 3479 - 3499
[39] Low Power 10T SRAM Cell with Improved Stability Solving Soft Error Issue
Lorenzo, Rohit
Paily, Roy
PROCEEDINGS OF THE 2019 IEEE REGION 10 CONFERENCE (TENCON 2019): TECHNOLOGY, KNOWLEDGE, AND SOCIETY, 2019, : 2554 - 2558
[40] Stability Analysis of a Novel Proposed Low Power 10T SRAM cell for Write Operation
Upadhyay, P.
Kar, R.
Mandal, D.
Ghoshal, S. P.
2014 FOURTH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING AND COMMUNICATION TECHNOLOGIES (ACCT 2014), 2014, : 112 - 117

← 1 2 3 4 5 →