HIGH-PERFORMANCE BULK CMOS TECHNOLOGY WITH MILLISECOND ANNEALING AND STRAINED SI

被引：0

作者：

Sugii, T. ^{[1
]}

Ikeda, K. ^{[1
]}

Miyashita, T. ^{[1
]}

机构：

[1] Fujitsu Labs Ltd, Tado, Mie, Japan

来源：

16TH IEEE INTERNATIONAL CONFERENCE ON ADVANCED THERMAL PROCESSING OF SEMICONDUCTORS - RTP 2008 | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

High-performance planar, bulk CMOS technology for 45nm nodes and beyond is reviewed from the point of mobility enhancement techniques and millisecond annealing techniques. Through continuous efforts to increase on-current with the strained techniques while scaling transistor dimensions with millisecond annealing, competitive high-end CMOS technology for 45nm node was realized.

引用

页码：37 / 42

页数：6

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