A multi-core memristor chip for Stochastic Binary STDP

This paper describes the design of a monolithic CMOS-memristive neuromorphic chip performing vector matrix multiplication between spike coded input vectors and the synaptic weights stored in the memristive array. A computing core including a 64x64 memristive array connecting 64 input and 64 output neurons has been fabricated. A Spiking Neural Network with a memristive synaptic layer exhibiting Stochastic Binary Spike-Time-Dependent-Plasticity has been experimentally demonstrated with the fabricated core. The CMOS-memristive neuromorphic processor is designed following a compact pseudo-CMOL design style that results in a modular and scalable computing core with a synaptic density of 22Ksynapses/mm(2). A single core has been fabricated in CEA-LETI 130nm CMOS-RRAM technology and its operation has been experimentally characterized. A multicore architecture with reconfigurable connectivity, where cores can be interconnected to either share pre-synaptic neurons and expand post-synaptic neurons, or vice versa, share postsynaptic neurons and expand pre-synaptic neurons, is proposed and presented here.