Modularity Driven Parallel Placement Algorithm for 2.5D FPGA Architectures

Interposer-based multi-die FPGAs comprise multiple dies interconnected externally via wires, enabling the creation of FPGA systems with greater capacity. These external connections are fewer in number than the internal interconnection network of a die and they also contribute to increased delay and wirelength. These architectural shifts necessitate placement and routing tools to strategically reduce the count of signals at the die boundary. Multi-die FPGA systems also offer substantial potential for design modularity, where each die can be optimized for specific functionalities. Adapting EDA tools to leverage these inherent device characteristics is imperative. Additionally, the modular nature of the system paves the way for parallelized implementations. Previous studies on multi-die FPGA placement have primarily concentrated on reducing signal crossings across die boundaries via global optimization. This strategy, however, incurs significant runtime demands, as it treats the multi-die FPGA as a unified fabric. This study presents a new methodology to partition and parallelize placement within a multi-die architecture. Our approach facilitates the optimization of partitioned nets without the reliance on a global optimization step. With netlist partitioning and adding virtual anchor blocks, the subcircuits can be placed on each die in parallel. The multi-die placer algorithm is integrated into the fast analytical placement tool 'Liquid'. A comprehensive performance comparison of our multi-die placer with the single-die monolithic implementation unveils similar quality results with improved runtime efficiency. Lastly, we compare our strategy to the widely-used academic placer, VPR, which relies on global optimization. The results demonstrate a 42x enhancement in runtime for lower estimations of Total Wirelength (TWL) and Critical Path Delay (CPD).