An 8-30 GHz High-Linearity Harmonic-Rejection Mixer in 45 nm CMOS SOI

This article presents a wideband mm-wave passive harmonic rejection mixer (HRM) operating at 8 to 30 GHz. Resistive scaling is used to maintain high mixer linearity while rejecting the third and fifth harmonic foldings. The clock generation circuit employs a passive two-stage polyphase filter (PPF) followed by a phase interpolator capacitor divider circuit to generate the eight-phases, which eliminates clock dividers and results in efficient operation up to 30 GHz. Furthermore, the clocks are designed with overlapping 50% duty cycle, and mixer cell-to-cell isolation is achieved using a Wilkinson network in the radio frequency (RF) path. This novel design results in mm-wave operation with wide instantaneous bandwidth and greatly reduced LO power consumption. The HRM is fabricated in Global Foundries 45RFSOI CMOS process and has a measured conversion loss of - 12.5 to - 15.5 dB at 8-30 GHz with an instantaneous IF bandwidth of up to 8 GHz. A harmonic rejection ratio (HRR) of 27-45 dB is measured across the entire bandwidth for the second, third and fifth harmonics. The measured input P1dB and IP3 are 4.2-7 and 14.2-16.2 dBm, respectively, at 8-30 GHz. The harmonic rejection is further seen in the mixer spur table, with measured spurs of - 70, - 70, - 60 dBm for the (2, 2), (2, 3) and (3, 3) spur for an LO frequency of 10 GHz, IF of 0.5 GHz and input signal power of 0 dBm. The total power consumption of the mixer is 200-390 mW at 8-30 GHz. This mixer is suitable for high linearity mm-wave 5G systems and wideband receivers and can be easily scaled to 20-50 GHz with similar low power consumption.