A 16 Path All-Passive Harmonic Rejection Mixer With Watt-Level In-Band IIP3 in 45-nm CMOS SOI

被引:6
|
作者
El-Aassar, Omar [1 ]
Kibaroglu, Kerim [1 ,2 ]
Rebeiz, Gabriel M. [1 ]
机构
[1] Univ Calif San Diego, Elect & Comp Engn Dept, San Diego, CA 92093 USA
[2] Movandi Corp, Newport Beach, CA 92660 USA
关键词
CMOS silicon-on-insulator (SOI); harmonic rejection mixer (HRM); high linearity; passive mixer; wideband receiver; RECEIVER;
D O I
10.1109/LMWC.2020.3004546
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work presents an all-passive harmonic rejection mixer (HRM) with watt-level in-band IIP3. The HRM operates in the voltage mode using resistors to scale the voltages of the different paths across the frequency cycle and therefore, attains very high linearity. The passive HRM employs a non-overlapping clock generation chain combined with duty cycle control circuit to trim the rise and fall times of the individual paths, and maintains the harmonic rejection ratio (HRR) over the frequency band. Two 0.13-3 GHz 16-path HRM chips are fabricated in 45-nm CMOS silicon-on-insulator (SOI) technology using thin and thick-oxide devices, respectively, with 80-MHz IF bandwidth and a core area 0.06 mm(2). The thick-oxide HRM achieves a HRR >35 dBc for all harmonics up to 3 GHz with a conversion loss of 8-10 dB, while the in-band IIP3 is 24-31 dBm and IP1 dB is 11-13 dBm for an RF of 0.5-3 GHz. To the authors knowledge, the all-passive 16-path HRM achieves the highest reported in-band IIP3 and IP1 dB.
引用
收藏
页码:790 / 793
页数:4
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