Investigation of Sub-20nm 4th generation DRAM cell transistor's parasitic resistance and scalable methodology for Sub-20nm era

The component of cell parasitic resistance at sub-20nm 4th generation DRAM cell transistor is investigated. To evaluate the cell characteristics, the Gate Buried Contact (GBC) to Active contact formation method with varied dopant concentrations was studied. We have discovered a scalable methodology that simultaneously reduces parasitic resistance and leakage with regard to Gate Induced Drain Leakage (GIDL). Also, we proved the importance of interface quality of Direct Contact on Cell (DCC) in order to reduce the parasitic resistance. The failure analysis is conducted by segmenting the resistance with Test Element Groups (TEGs) at wafer level. And the process windows and local variations from fabricated devices are electrically verified by core failure analysis. Through this investigation, we proposed the scalable methodology that can sustain generational scalability of DRAM.