Interface Stress Analysis Based on Warpage Characterization in a Flip-Chip Package

被引:1
|
作者
Zhong, Cheng [1 ,2 ]
Li, Chenglong [1 ,2 ]
Jiang, Ruoyu [1 ,2 ]
Li, Yulong [1 ,2 ]
Peng, Xu [1 ,2 ]
Lu, Jibao [1 ,2 ]
Ren, Linlin [1 ]
Sun, Rong [1 ]
机构
[1] Chinese Acad Sci, Shenzhen Inst Adv Technol, Shenzhen Inst Adv Elect Mat, Shenzhen 518055, Peoples R China
[2] Chinese Acad Sci Shenzhen, Shenzhen Inst Adv Technol, Shenzhen 518055, Peoples R China
基金
中国国家自然科学基金; 国家重点研发计划;
关键词
Warpage; flip chip; finite element analysis (FEA); interface stress; DEGRADATION;
D O I
10.1109/ICEPT56209.2022.9873419
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
For the package structure, the internal components of the package need to be collaboratively deformed when the temperature changes and the package's surface will be commonly expressed in a concave or convex shape, i.e., warpage will happen in the package. The warpage of the package is usually easier to obtain through experimental characterization. Considering that the stress and strain inside the package are closely related to the warpage of the overall structure, it is theoretically feasible to calculate the internal stress distribution in the package through accurate and complete warpage information. As a result, it might be used for evaluating the potential failure risk in the package in advance. Especially, it will be very valuable for some expensive packages to evaluate the internal stress without damaging the package. However, the related research is still lacking. In this paper, we combine finite element analysis (FEA) and experiment to accurately record and reproduce the warpage evolution during the whole process of temperature changing. Then accurate material property and boundary conditions are obtained in FEA. After that, the interface stress of thermal interface material (TIM) and underfill are analyzed in detail. This study provides a new method for evaluating the failure risk of thermal-mechanical stress of materials in the package and may also be applied for stress analysis in other package structures.
引用
收藏
页数:6
相关论文
共 50 条
  • [21] JACS-Pak™ flip-chip Chip Scale Package development and characterization
    Lindsey, SE
    Aday, J
    Blood, B
    Guo, YF
    Hemann, B
    Kellar, J
    Koehler, C
    Liu, J
    Sarihan, V
    Tessier, T
    Thompson, L
    Yeung, B
    48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS, 1998, : 511 - 517
  • [22] Development of thin flip-chip BGA for package on package
    Suzuki, Yasuhiro
    Kayashima, Yuuji
    Maeda, Takehik
    Matsuura, Yoshihiro
    Sekiguchi, Tomobisa
    Watanabe, Akio
    57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS, 2007, : 8 - +
  • [23] A Theoretical Solution for Thermal Warpage of Flip-Chip Packages
    Tsai, Ming-Yi
    Wang, Yu-Wen
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2020, 10 (01): : 72 - 78
  • [24] The effect of underfill epoxy on warpage in flip-chip assemblies
    Zhang, WG
    Wu, D
    Su, BZ
    Hareb, SA
    Lee, YC
    Masterson, BP
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART A, 1998, 21 (02): : 323 - 329
  • [25] Finite Element Analysis of Copper Pillar Interconnect Stress of Flip-chip Chip-Scale Package
    Afripin, Amirul
    Carpenter, Burt
    Hauck, Torsten
    2021 22ND INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 2021,
  • [26] Lock-in Thermography for Flip-chip Package Failure Analysis
    Cao, Lihong
    Venkata, Manasa
    Huynh, Jeffery
    Tan, Joseph
    Tay, Meng-Yeow
    Qiu, Wen
    Wadhwa, Kannu
    Schlangen, Rudolf
    ISTFA 2012: CONFERENCE PROCEEDINGS FROM THE 38TH INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, 2012, : 316 - 324
  • [27] Analysis of Thin Flip Chip Chip-Scale Package Warpage Causes and Variations
    Foong, C. S.
    Afripin, Amirul
    Lakhera, Nishant
    Uehling, Trent
    PROCEEDINGS OF THE IEEE 74TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC 2024, 2024, : 1286 - 1292
  • [28] Warpage Improvement for Large Die Flip Chip Package
    Xiong, Bingshou
    Lee, Myung-June
    Kao, Thomas
    2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), 2009, : 40 - +
  • [29] Reliability study of the laminate-based flip-chip chip scale package
    Matsuda, Y
    Takai, T
    Okada, Y
    Lall, P
    Koehler, C
    Tessler, T
    Olsen, D
    2ND 1998 IEMT/IMC SYMPOSIUM, 1998, : 40 - 44
  • [30] Electrical Characteristics of Flip-Chip Package Interconnection
    Li, Hongbin
    Zhao, Quanming
    Zuo, Panpan
    2016 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC), 2016, : 1003 - 1005