An Efficient Hardware Accelerator of High-Speed NTT for CRYSTALS-Kyber Post-Quantum Cryptography

被引:0
|
作者
Zhang, Zhuoyao [1 ]
Cui, Yijun [1 ]
Ni, Ziying [2 ]
Wang, Chenghua [1 ]
Liu, Weiqiang [1 ]
机构
[1] Nanjing Univ Aeronaut & Astronaut, Coll Elect & Informat Engn, Nanjing, Peoples R China
[2] Queens Univ Belfast, CSIT, Belfast, Antrim, North Ireland
来源
FIFTY-SEVENTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, IEEECONF | 2023年
基金
中国国家自然科学基金;
关键词
post-quantum cryptography; number theoretic transform; CRYSTALS-Kyber; hardware implementation;
D O I
10.1109/IEEECONF59524.2023.10477061
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
CRYSTALS-Kyber (Kyber) is the sole chosen Public-key Encryption (PKE) and key-establishment algorithm in the finalist round of the Post-quantum Cryptography (PQC) standardization initiated by the National Institute of Standards and Technology (NIST). Within the Kyber protocol, the Number Theoretic Transform (NTT) operation stands out as the most critical and time-intensive component, requiring rapid butterfly units and efficient memory approaches. This paper proposes a high-speed NTT architecture featuring a novel butterfly operation unit tailored for the Kyber protocol, capable of supporting high-frequency operations and effective memory approaches. The proposed NTT structure is realized on the Xilinx Artix-7 FPGA to assess its performance. Experimental results demonstrate that the proposed NTT design can execute the NTT operation in 459 cycles at 314MHz using only 640 LUTs, 667 FFs, and 2 DSPs, offering a more than 24% improvement compared to state-of-the-art designs.
引用
收藏
页码:1 / 6
页数:6
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