FPGA-Based High-Performance Network Impairment Emulator

被引:0
|
作者
Duan, Dexuan [1 ,2 ]
Wang, Xinshuo [1 ,2 ]
Li, Lin [1 ,2 ]
Liu, Lei [1 ,2 ]
机构
[1] Chinese Acad Sci, Inst Acoust, Natl Network New Media Engn Res Ctr, 21 North Fourth Ring Rd, Beijing 100190, Peoples R China
[2] Univ Chinese Acad Sci, Sch Elect Elect & Commun Engn, 19 A Yuquan Rd, Beijing 100049, Peoples R China
来源
ELECTRONICS | 2024年 / 13卷 / 24期
关键词
FPGA; impairment; network; WAN emulation;
D O I
10.3390/electronics13244998
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
With the rapid growth of Wide Area Networks (WANs) and advancements in 5G, cloud computing, and IoT, networks face higher demands for low cost, high capacity, reliability, and security. To ensure these requirements, network impairment emulators have become essential tools for testing and optimizing network performance under various conditions. This paper presents an FPGA-based Network Impairment Emulator (FNIE) that accurately emulates packet loss, reordering, and delay with high throughput and low cost. FNIE can achieve up to 100 Gbps throughput, with a configurable packet loss rate ranging from 0.001% to 100%, with a resolution as fine as 0.001%. It also supports up to 64 descriptor queues for reordering, a maximum reordering extent of 511, and emulates delays from 1 mu s to 1 s.
引用
收藏
页数:14
相关论文
共 50 条
  • [31] FPGA-Based Design Of a High-Performance and Modular Video Processing Platform
    Desmouliers, Christophe
    Oruklu, Erdal
    Saniie, Jafar
    2009 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY, 2009, : 391 - 396
  • [32] An FPGA-Based Hardware Emulator for Neuromorphic Chip With RRAM
    Luo, Tao
    Wang, Xuan
    Qu, Chuping
    Lee, Matthew Kay Fei
    Tang, Wai Teng
    Wong, Weng-Fai
    Goh, Rick Siow Mong
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (02) : 438 - 450
  • [33] An FPGA-based hardware emulator for fast fault emulation
    Hong, JH
    Hwang, SA
    Wu, CW
    PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 345 - 348
  • [34] FPGA-based hardware accelerator for high-performance data-stream processing
    Lysakov K.F.
    Shadrin M.Y.
    Pattern Recognition and Image Analysis, 2013, 23 (1) : 26 - 34
  • [35] A New High-Performance Scalable Dynamic Interconnection for FPGA-based Reconfigurable Systems
    Jovanovic, Slavisa
    Tanougast, Camel
    Weber, Serge
    2008 INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2008, : 61 - 66
  • [36] High-performance computing for SKA transient search: Use of FPGA-based accelerators
    Aafreen, R.
    Abhishek, R.
    Ajithkumar, B.
    Vaidyanathan, Arunkumar M.
    Barve, Indrajit V.
    Bhattramakki, Sahana
    Bhat, Shashank
    Girish, B. S.
    Ghalame, Atul
    Gupta, Y.
    Hayatnagarkar, Harshal G.
    Kamini, P. A.
    Karastergiou, A.
    Levin, L.
    Madhavi, S.
    Mekhala, M.
    Mickaliger, M.
    Mugundhan, V.
    Naidu, Arun
    Oppermann, J.
    Pandian, B. Arul
    Patra, N.
    Raghunathan, A.
    Roy, Jayanta
    Sethi, Shiv
    Shaw, B.
    Sherwin, K.
    Sinnen, O.
    Sinha, S. K.
    Srivani, K. S.
    Stappers, B.
    Subrahmanya, C. R.
    Prabu, Thiagaraj
    Vinutha, C.
    Wadadekar, Y. G.
    Wang, Haomiao
    Williams, C.
    JOURNAL OF ASTROPHYSICS AND ASTRONOMY, 2023, 44 (01)
  • [37] HashCache: High-Performance State Tracking for Resilient FPGA-based Packet Processing
    Offel, Michael
    Ley, Andreas
    Hager, Sven
    2023 33RD INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL, 2023, : 364 - 364
  • [38] High-performance computing for SKA transient search: Use of FPGA-based accelerators
    R. Aafreen
    R. Abhishek
    B. Ajithkumar
    Arunkumar M. Vaidyanathan
    Indrajit V. Barve
    Sahana Bhattramakki
    Shashank Bhat
    B. S. Girish
    Atul Ghalame
    Y. Gupta
    Harshal G. Hayatnagarkar
    P. A. Kamini
    A. Karastergiou
    L. Levin
    S. Madhavi
    M. Mekhala
    M. Mickaliger
    V. Mugundhan
    Arun Naidu
    J. Oppermann
    B. Arul Pandian
    N. Patra
    A. Raghunathan
    Jayanta Roy
    Shiv Sethi
    B. Shaw
    K. Sherwin
    O. Sinnen
    S. K. Sinha
    K. S. Srivani
    B. Stappers
    C. R. Subrahmanya
    Thiagaraj Prabu
    C. Vinutha
    Y. G. Wadadekar
    Haomiao Wang
    C. Williams
    Journal of Astrophysics and Astronomy, 44
  • [39] FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data
    Roy, Sujoy Sinha
    Turan, Furkan
    Jarvinen, Kimmo
    Vercauteren, Frederik
    Verbauwhede, Ingrid
    2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2019, : 387 - 398
  • [40] A high-performance FPGA-based BWA-MEM DNA sequence alignment
    Pham-Quoc, Cuong
    Kieu-Do, Binh
    Thinh, Tran Ngoc
    CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2021, 33 (02):