One-hot residue coding for low delay-power product CMOS design

被引：0
|
作者：
Grand Valley State Univ, Grand Rapids, United States [1 ]
机构：
来源：
IEEE Trans Circuits Syst II Analog Digital Signal Process | / 3卷 / 303-313期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [21] DESIGN OF AN EFFICIENT PARALLEL COMPARATOR ARCHITECTURE FOR LOW POWER DELAY PRODUCT
    Gupta, Mangal Deep
    Chauhan, Rajeev Kumar
    ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING, 2021, 19 (02) : 155 - 167
  • [22] Power and delay macro-modeling for submicronic CMOS process: Application to low power design
    Auvergne, D
    Daga, JM
    Turgis, S
    MICROELECTRONIC ENGINEERING, 1997, 39 (1-4) : 209 - 223
  • [23] A low power-delay product page-based address bus coding method
    Tsai, CM
    Liao, GW
    Lin, RB
    16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2003, : 521 - 526
  • [24] Exploring a Circuit Design Approach based on One-hot Multi-valued Domino Logic
    Gope, Dibakar
    Lin, Pey-Chang Kent
    Khatri, Sunil P.
    53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 69 - 72
  • [25] An Optimization Algorithm for Simultaneous Routing and Buffer Insertion with Delay-Power Constraints in VLSI Layout Design
    Uttraphan, C.
    Shaikh-Husin, N.
    Hani, M. Khalil
    PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014), 2015, : 357 - +
  • [26] Low power CMOS design challenges
    Kuroda, T.
    IEICE Transactions on Electronics, 2001, E84-C (08) : 1021 - 1028
  • [27] Design methodology of CMOS low power
    Hao Dongyan
    Zhang Ming
    Zheng Wei
    2005 IEEE International Conference on Industrial Technology - (ICIT), Vols 1 and 2, 2005, : 178 - 182
  • [28] Low power CMOS design challenges
    Kuroda, T
    IEICE TRANSACTIONS ON ELECTRONICS, 2001, E84C (08): : 1021 - 1028
  • [29] The Delay-Power Tradeoff of Low Complexity Cross-Layer Scheduling: When Lyapunov Meets Markov
    Xie, Zhanyuan
    Chen, Wei
    IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC 2022), 2022, : 1227 - 1232
  • [30] Low-power-delay-product radix-4 8*8 Booth multiplier in CMOS
    Xue, H.
    Patel, R.
    Boppana, N. V. V. K.
    Ren, S.
    ELECTRONICS LETTERS, 2018, 54 (06) : 344 - +
12345