Test Generation for Stuck-on Faults in Pass-Transistor Logic SPL and Implementation of DFT Circuits

被引：0
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作者：
Shinogi, Tsuyoshi
Hayashi, Terumine
Taki, Kazuo
机构：
[1] Graduate School of Engineering, Mie University, Tsu, 514-8507, Japan
[2] Faculty of Engineering, Kobe University, Kobe, 657-8501, Japan
来源：
Systems and Computers in Japan | 1999年 / 30卷 / 07期
关键词：
D O I：
10.1002/(SICI)1520-684X(19990630)30:73.0.CO;2-9
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学科分类号：
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页码：55 / 67
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