ARRAY LAYOUT METHODOLOGY FOR VLSI CIRCUITS.

被引：0
|
作者：
Krishnan, Musaravakkam S. [1 ]
Hayes, John P. [1 ]
机构：
[1] Xerox Corp, El Segundo, CA, USA, Xerox Corp, El Segundo, CA, USA
来源：
| 1600年 / C-35期
关键词：
ARRAY LAYOUT METHODOLOGY - CARRY-SAVE ADDERS - CUBE-CONNECTED CYCLES - LAYOUT SLICES;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [21] Array optimization algorithm for VLSI layout
    Xu, Dongmin
    Chen, Yunkang
    Qinghua Daxue Xuebao/Journal of Tsinghua University, 1995, 35 (02): : 1 - 9
  • [22] Timing, power and noise optimization for simultaneous switching in VLSI circuits.
    Shiue, WT
    6TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XV, PROCEEDINGS: MOBILE/WIRELESS COMPUTING AND COMMUNICATION SYSTEMS III, 2002, : 462 - 465
  • [23] MODELING OF LITHOGRAPHY RELATED YIELD LOSSES FOR CAD OF VLSI CIRCUITS.
    Maly, Wojciech
    1600, (CAD-4):
  • [24] Physical Limitations and Technological Barriers in Development of MOS VLSI Circuits.
    Jakubowski, Andrzej
    Swit, Alfred
    Elektronika Warszawa, 1984, 25 (06): : 14 - 22
  • [25] VALIDATION OF LATCH-UP MITIGATION IN COMPLEX VLSI CIRCUITS.
    Criscuolo, J.A.
    Cable, J.S.
    Lee, D.C.
    IEEE Transactions on Nuclear Science, 1986, NS-33 (06)
  • [26] ESD PROTECTION - DESIGN AND LAYOUT ISSUES FOR VLSI CIRCUITS
    DUVVURY, C
    ROUNTREE, RN
    MCPHEE, RA
    IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 1989, 25 (01) : 41 - 47
  • [27] VLSI circuits with fractal layout for spatial image decorrelation
    Rovetta, Stefano
    Zunino, Rodolfo
    Proceedings - IEEE International Symposium on Circuits and Systems, 1999, 4
  • [28] VLSI circuits with fractal layout for spatial image decorrelation
    Rovetta, S
    Zunino, R
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4: IMAGE AND VIDEO PROCESSING, MULTIMEDIA, AND COMMUNICATIONS, 1999, : 110 - 113
  • [29] METHODOLOGY FOR WORST-CASE ANALYSIS OF INTEGRATED CIRCUITS.
    Nassif, Sani R.
    Strojwas, Andrzej J.
    Director, Stephen W.
    1600, (CAD-5):
  • [30] Modified Standard Cell Methodology for VLSI Layout Compaction
    Chavez-Martinez, E. J.
    Chavez-Martinez, M.
    Gurrola-Navarro, M. A.
    2012 9TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTING SCIENCE AND AUTOMATIC CONTROL (CCE), 2012,
12345