Selecting partial scan flip-flops for circuit partitioning

被引：0
|
作者：
Ono, Toshinobu [1 ]
机构：
[1] NEC Corp, Kawasaki, Japan
来源：
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1994年
关键词：
Circuit partitioning - Dependency graph - Scan flip flop - Subcircuits - Test pattern generator - Testability;
D O I：
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中图分类号：
学科分类号：
摘要：
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页码：646 / 650
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