Level Converting Scan Flip-Flops

Power consumption is an important issue in nanoscale circuits. The multiple supply voltages (MW) technique, where non-critical parts are supplied with the lower supply voltage, can be used to balance power and performance, as both dynamic and leakage power are reduced with the lower supply voltage. However, level converting circuits must be inserted between different voltage domains to avoid leakage current. In this paper, we present three scan flip-flop designs that support a low-power mechanism, including level converting and sleep mode operation. The designs provide tradeoff between power and speed, and thus provide a simple and efficient way to design low-power high-testability circuits.