Design-for-testability for path delay faults in large combinational circuits using test points

被引：0
|
作者：
Univ of Iowa, Iowa City, United States [1 ]
机构：
来源：
IEEE Trans Comput Aided Des Integr Circuits Syst | / 4卷 / 333-343期
基金：
美国国家科学基金会;
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [41] A method of test generation for path delay faults in balanced sequential circuits
    Ohtake, S
    Miwa, S
    Fujiwara, H
    20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2002, : 321 - 327
  • [42] Statistical Modeling of Combinational Circuits Using Path Based Delay Analysis
    Siddhasen R. Patil
    D. K. Gautam
    Silicon, 2018, 10 : 2063 - 2069
  • [43] Statistical Modeling of Combinational Circuits Using Path Based Delay Analysis
    Patil, Siddhasen R.
    Gautam, D. K.
    SILICON, 2018, 10 (05) : 2063 - 2069
  • [44] Design-for-testability for reversible logic circuits based on bit-swapping
    Mondal, Joyati
    Das, Debesh Kumar
    Bhattacharya, Bhargab
    IET QUANTUM COMMUNICATION, 2024, 5 (02): : 113 - 122
  • [45] Design-for-testability for synchronous sequential circuits that maintains functional switching activity
    Pomeranz, Irith
    Reddy, Sudhakar M.
    21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 181 - +
  • [46] DIFFERENTIAL BICMOS LOGIC-CIRCUITS - FAULT CHARACTERIZATION AND DESIGN-FOR-TESTABILITY
    HESSABI, S
    OSMAN, MY
    ELMASRY, MI
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1995, 3 (03) : 437 - 445
  • [47] Testing and Design-for-Testability Techniques for 3D Integrated Circuits
    Noia, Brandon
    Chakrabarty, Krishnendu
    2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, : 474 - 479
  • [48] Methodology to Design-For-Testability Automation for Mixed-Signal Integrated Circuits
    Mosin, Sergey
    PROCEEDINGS OF IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS 2013), 2013,
  • [49] Design-for-testability and test of DF-FPDLMS adaptive filter
    School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 610054, China
    不详
    Dianzi Keji Diaxue Xuebao, 2007, 4 (740-743):
  • [50] Differential Scan-Path: A Novel Solution for Secure Design-for-Testability
    Manich, S.
    Wamser, Markus S.
    Guillen, Oscar M.
    Sigl, G.
    2013 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2013,
12345