SAMPLE-AND-HOLD CIRCUIT WITH ENHANCED LINEARITY.

被引：0

作者：

Plekhanov, V.S. ^{[1
]}

Sidorov, V.M. ^{[1
]}

Shakhtsheider, V.G. ^{[1
]}

机构：

[1] Novosibirsk Electrical Engineering, Inst, Novosibirsk, USSR, Novosibirsk Electrical Engineering Inst, Novosibirsk, USSR

来源：

| 1600年 / 28期

关键词：

DATA CONVERSION; ANALOG TO DIGITAL - Equipment - ELECTRONIC CIRCUITS; DIGITAL; -; Applications;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A sample-and-hold circuit designed for use with general-purpose analog-digital converters is described. The circuit has a sampling time of 0. 5 mu equals sec, a decay rate of less than equivalent to 0. 15 v/sec under normal conditions, an output-signal variation of plus or minus 3 v, an error of less than equivalent to 0. 1%, and a supply-instability suppression factor of greater than equivalent to 65 db.

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