SAMPLE-AND-HOLD CIRCUIT WITH ENHANCED LINEARITY.

被引：0

作者：

Plekhanov, V.S. ^{[1
]}

Sidorov, V.M. ^{[1
]}

Shakhtsheider, V.G. ^{[1
]}

机构：

[1] Novosibirsk Electrical Engineering, Inst, Novosibirsk, USSR, Novosibirsk Electrical Engineering Inst, Novosibirsk, USSR

来源：

| 1600年 / 28期

关键词：

DATA CONVERSION; ANALOG TO DIGITAL - Equipment - ELECTRONIC CIRCUITS; DIGITAL; -; Applications;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A sample-and-hold circuit designed for use with general-purpose analog-digital converters is described. The circuit has a sampling time of 0. 5 mu equals sec, a decay rate of less than equivalent to 0. 15 v/sec under normal conditions, an output-signal variation of plus or minus 3 v, an error of less than equivalent to 0. 1%, and a supply-instability suppression factor of greater than equivalent to 65 db.

引用

共 50 条

[1] SAMPLE-AND-HOLD CIRCUIT WITH ENHANCED LINEARITY
PLEKHANOV, VS
SIDOROV, VM
SHAKHTSHNEIDER, VG
INSTRUMENTS AND EXPERIMENTAL TECHNIQUES, 1985, 28 (04) : 828 - 829
[2] Sample-and-Hold Circuit.
Linder, Norbert
Elektronik Munchen, 1981, 30 (24): : 74 - 75
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STAMPER, H
ELECTRONIC ENGINEERING, 1968, 40 (484): : 342 - &
[4] AN ACCURATE CMOS SAMPLE-AND-HOLD CIRCUIT
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (01) : 120 - 122
[5] ACQUISITION ERROR IN SAMPLE-AND-HOLD CIRCUIT
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ELECTRONICS LETTERS, 2005, 41 (09) : 520 - 522
[7] OPTICALLY STROBED SAMPLE-AND-HOLD CIRCUIT
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[8] Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit
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MECHANICAL ENGINEERING, INTELLIGENT SYSTEM AND APPLIED MECHANICS, 2014, 473 : 50 - +
[9] A switched-current sample-and-hold circuit
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ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 1, 1996, : 191 - 194
[10] PEAK SAMPLE-AND-HOLD CIRCUIT FOR CONTROL AND MEASUREMENT
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INSTRUMENT PRACTICE, 1971, 25 (06): : 336 - &

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