共 50 条
- [31] A programmable parallel VLSI architecture for 2-D discrete wavelet transform JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2001, 28 (03): : 151 - 163
- [32] VLSI systolic array architecture for the lattice structure of the discrete wavelet transform ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 605 - 608
- [33] VLSI Implementation of Discrete Wavelet Transform using Systolic Array Architecture Advances in Computer and Informatiom Sciences and Engineering, 2008, : 467 - 472
- [35] A high-performance tree-block pipelining architecture for separable 2-D inverse discrete wavelet transform IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2003, E86D (10): : 1966 - 1975
- [36] An efficient line-based architecture for 2-D discrete wavelet transform 2005 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS: VOL 1: COMMUNICATION THEORY AND SYSTEMS, 2005, : 1322 - 1325
- [39] A parallel architecture for the 2-D discrete wavelet transform with integer lifting scheme JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2001, 28 (03): : 165 - 185
- [40] A Parallel Architecture for the 2-D Discrete Wavelet Transform with Integer Lifting Scheme Journal of VLSI signal processing systems for signal, image and video technology, 2001, 28 : 165 - 185