Systolic array architecture for 2-D inverse wavelet transform

被引:0
|
作者
Singh, J. [1 ]
Antoniou, A. [1 ]
Shpak, D.J. [1 ]
机构
[1] Univ of Victoria, Victoria, Canada
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:193 / 196
相关论文
共 50 条
  • [21] A Reconfigurable Architecture for 1-D and 2-D Discrete Wavelet Transform
    Sun, Qing
    Jiang, Jiang
    Zhu, Yongxin
    Fu, Yuzhuo
    2013 IEEE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), 2013, : 81 - 84
  • [22] An efficient architecture for 2-D biorthogonal inverse discrete wavelet transforms
    Yu, C
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2003, 49 (02) : 427 - 432
  • [23] Efficient VLSI architecture for 2-D inverse discrete wavelet transforms
    Yu, C
    Chen, SJ
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING, 1999, : 524 - 527
  • [24] A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform
    Chien-Yu Chen
    Zhong-Lan Yang
    Tu-Chih Wang
    Liang-Gee Chen
    Journal of VLSI signal processing systems for signal, image and video technology, 2001, 28 : 151 - 163
  • [25] Memory-Efficient Architecture of 2-D Discrete Wavelet Transform
    Hao Y.
    Zhang Y.
    Zhang W.
    Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University, 2022, 56 (01): : 177 - 183
  • [26] A VLSI architecture for a fast computation of the 2-D discrete wavelet transform
    Zhang, Chengjun
    Wang, Chunyan
    Ahmad, M. Omair
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 3980 - 3983
  • [27] A novel efficient VLSI architecture of 2-D discrete wavelet transform
    Hsieh, Chin-Fa
    Tsai, Tsung-Han
    Lai, Chih-Hung
    Shan, Tai-An
    2008 FOURTH INTERNATIONAL CONFERENCE ON INTELLIGENT INFORMATION HIDING AND MULTIMEDIA SIGNAL PROCESSING, PROCEEDINGS, 2008, : 647 - 650
  • [28] VLSI ARCHITECTURE FOR 2-D DAUBECHIES WAVELET TRANSFORM WITHOUT MULTIPLIERS
    LEWIS, AS
    KNOWLES, G
    ELECTRONICS LETTERS, 1991, 27 (02) : 171 - 173
  • [29] A distributed memory and control architecture for 2-D discrete wavelet transform
    Singh, J
    Antoniou, A
    Shpak, DJ
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING, 1999, : 387 - 390
  • [30] A scalable pipelined architecture for separable 2-D discrete wavelet transform
    Jou, JM
    Chen, PY
    Shiau, YH
    Liang, MS
    PROCEEDINGS OF ASP-DAC '99: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1999, 1999, : 205 - 208