共 50 条
- [1] Systolic Array Based VLSI Architecture For High Throughput 2-D Discrete Wavelet Transform 2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2016, : 100 - 103
- [2] A systolic array architecture for 2-D discrete Hartley transform 6TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XIII, PROCEEDINGS: CONCEPTS AND APPLICATIONS OF SYSTEMICS, CYBERNETICS AND INFORMATICS III, 2002, : 434 - 440
- [3] A high speed array architecture for 2-D wavelet transform PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 1239 - 1242
- [6] A scalable architecture for 2-D discrete wavelet transform VLSI SIGNAL PROCESSING, IX, 1996, : 369 - 377
- [7] A novel FPGA architecture of a 2-D Wavelet Transform JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2006, 42 (03): : 273 - 284
- [8] A new architecture for the 2-D discrete wavelet transform 1997 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2: PACRIM 10 YEARS - 1987-1997, 1997, : 481 - 484
- [9] A Novel FPGA Architecture of a 2-D Wavelet Transform Journal of VLSI signal processing systems for signal, image and video technology, 2006, 42 : 273 - 284
- [10] Systolic Architecture for Implementation of 2-D Discrete Sine Transform INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY AND SYSTEM DESIGN 2011, 2012, 30 : 441 - 448