Simulation study of dispatch rules for reducing flow times in semiconductor wafer fabrication

被引：0

作者：

Hung, Yi-Feng ^{[1
]}

Chen, Ing-Ren ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Hsinchu, Taiwan

来源：

| 1998年 / Taylor & Francis Ltd, London, United Kingdom卷 / 09期

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