共 50 条
- [1] MODELING FOR STUCK FAULTS IN CMOC NON-THRESHOLD LOGIC (NTL) COMBINATIONAL-CIRCUITS MICROELECTRONICS AND RELIABILITY, 1995, 35 (04): : 669 - 681
- [2] TESTING FOR STUCK FAULTS IN CMOS COMBINATIONAL-CIRCUITS IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1991, 138 (02): : 191 - 197
- [6] Modeling and testing for stuck faults in pseudo nMOS combinational circuits MICROELECTRONICS AND RELIABILITY, 1996, 36 (05): : 685 - 692
- [7] Modeling and testing for stuck faults in pseudo nMOS combinational circuits Microelectron Reliab, 5 (685-692):
- [8] EXHAUSTIVE TESTING OF STUCK-OPEN FAULTS IN CMOS COMBINATIONAL-CIRCUITS IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1988, 135 (01): : 10 - 16
- [9] A NEW APPROACH TO DERIVE ROBUST-TESTS FOR STUCK-OPEN FAULTS IN CMOS COMBINATIONAL LOGIC-CIRCUITS 26TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, 1989, : 726 - 729