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- [31] Reducing SoC test time and test power in hierarchical scan test: Scan architecture and algorithms 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 351 - +
- [34] Reducing average and peak test power through scan chain modification JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (04): : 457 - 467
- [35] Reducing power dissipation during test using scan chain disable 19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2001, : 319 - 324
- [36] A routability constrained scan chain ordering technique for test power reduction* ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 648 - 652
- [37] Reducing Average and Peak Test Power Through Scan Chain Modification Journal of Electronic Testing, 2003, 19 : 457 - 467
- [39] Test scheduling and scan-chain division under power constraint 10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 259 - 264
- [40] Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes Journal of Electronic Testing, 2004, 20 : 199 - 212