共 50 条
- [21] A Generic Framework for Scan Capture Power Reduction in Test Compression Environment 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, : 1055 - 1055
- [22] Low power test compression technique for designs with multiple scan chains 14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 386 - 389
- [23] A compression improvement technique for low-power scan test data TENCON 2006 - 2006 IEEE REGION 10 CONFERENCE, VOLS 1-4, 2006, : 1835 - +
- [24] On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques IEICE TRANSACTIONS ON ELECTRONICS, 2010, E93C (03): : 369 - 378
- [25] Compression/scan co-design for reducing test data volume, scan-in power dissipation and test application time 11TH PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS, 2005, : 175 - 182
- [27] Automated Optimization of Scan Chain Structure for Test Compression-Based Designs 2016 IEEE 25TH ASIAN TEST SYMPOSIUM (ATS), 2016, : 185 - 190
- [28] Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 59 - 64