W versus Co-al as gate fill-metal for aggressively scaled replacement high-k/metal gate devices for (sub-)22nm technology nodes

被引：0

作者：

Veloso, Anabela ^{[1
]}

Chew, Soon Aik ^{[1
]}

Schram, Tom ^{[1
]}

Dekkers, Harold ^{[1
]}

Van Ammel, Annemie ^{[1
]}

Witters, Thomas ^{[1
]}

Tielens, Hilde ^{[1
]}

Heylen, Nancy ^{[1
]}

Devriendt, Katia ^{[1
]}

Sebaai, Farid ^{[1
]}

Brus, Stephan ^{[1
]}

Ragnarsson, Lars-Ake ^{[1
]}

Pantisano, Luigi ^{[1
]}

Eneman, Geert ^{[1
]}

Carbonell, Laure ^{[1
]}

Richard, Olivier ^{[1
]}

Favia, Paola ^{[1
]}

Geypen, Jef ^{[1
]}

Bender, Hugo ^{[1
]}

Higuchi, Yuichi ^{[2
]}

Phatak, Anup ^{[3
]}

Thean, Aaron ^{[1
]}

Horiguchi, Naoto ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Assignee at IMEC from Panasonic, Kapeldreef 75, B-3001 Leuven, Belgium

[3] Assignee at IMEC from Applied Materials Belgium NV, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

Japanese Journal of Applied Physics | 2013年 / 52卷 / 4 PART 2期

关键词：

Bias temperature instability - Comprehensive evaluation - Gate resistance - High-k/metal gates - Intrinsic stress - Low threshold voltage - Materials selection - Technology nodes;

D O I：

04CA03

中图分类号：

学科分类号：

摘要：

引用

共 36 条

[31] FMAX / VMIN and noise margin impacts of aging on domino read, static write, and retention of 8T 1R1W SRAM arrays in 22nm high-k/metal-gate tri-gate CMOS
Kulkarni, Jaydeep P.
Tokunaga, Carlos
Cho, Minki
Khellah, Muhammad M.
Tschanz, James W.
De, Vivek K.
2017 SYMPOSIUM ON VLSI CIRCUITS, 2017, : C116 - C117
[32] A scaled floating body cell (FBC) memory with high-k plus metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond
Ban, Ibrahim
Avci, Uygar E.
Kencke, David L.
Chang, Peter L. D.
2008 SYMPOSIUM ON VLSI TECHNOLOGY, 2008, : 71 - +
[33] A scaled floating body cell (FBC) memory with High-k plus metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond
Ban, Ibrahim
Avci, Uygar E.
Kencke, David L.
Chang, Peter L. D.
2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, : 92A - 93A
[34] Replacement High-K/Metal-Gate High-Ge-Content Strained SiGe FinFETs with High Hole Mobility and Excellent SS and Reliability at Aggressive EOT ∼7Å and Scaled Dimensions Down to Sub-4nm Fin Widths
Hashemi, P.
Ando, T.
Balakrishnan, K.
Cartier, E.
Lofaro, M.
Ott, J. A.
Bruley, J.
Lee, K. -L.
Koswatta, S.
Dawes, S.
Rozen, J.
Pyzyna, A.
Chan, K.
Engelmann, S. U.
Park, D. -G.
Narayanan, V.
Mo, R. T.
Leobandung, E.
2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2016,
[35] High performance pMOSFETs using Si/Si1-xGex/Si quantum wells with high-k/metal gate stacks and additive uniaxial strain for 22 nm technology node
Suthram, S.
Majhi, P.
Sun, G.
Kalra, P.
Harris, H. R.
Choi, K. J.
Heh, D.
Oh, J.
Kelly, D.
Choi, R.
Cho, B. J.
Hussain, M. M.
Smith, C.
Banerjee, S.
Tsai, W.
Thompson, S. E.
Tseng, H. H.
Jammy, R.
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 727 - +
[36] A Novel Damage-Free High-k Etch Technique Using Neutral Beam-Assisted Atomic Layer Etching (NBALE) for Sub-32nm Technology Node Low Power Metal Gate/High-k Dielectric CMOSFETs
Min, K. S.
Kang, C. Y.
Park, C.
Park, C. S.
Park, B. J.
Park, J. B.
Hussain, M. M.
Lee, Jack C.
Lee, B. H.
Kirsch, P.
Tseng, H-H
Jammy, R.
Yeom, G. Y.
2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 406 - +

← 1 2 3 4 →