W versus Co-al as gate fill-metal for aggressively scaled replacement high-k/metal gate devices for (sub-)22nm technology nodes

被引：0

作者：

Veloso, Anabela ^{[1
]}

Chew, Soon Aik ^{[1
]}

Schram, Tom ^{[1
]}

Dekkers, Harold ^{[1
]}

Van Ammel, Annemie ^{[1
]}

Witters, Thomas ^{[1
]}

Tielens, Hilde ^{[1
]}

Heylen, Nancy ^{[1
]}

Devriendt, Katia ^{[1
]}

Sebaai, Farid ^{[1
]}

Brus, Stephan ^{[1
]}

Ragnarsson, Lars-Ake ^{[1
]}

Pantisano, Luigi ^{[1
]}

Eneman, Geert ^{[1
]}

Carbonell, Laure ^{[1
]}

Richard, Olivier ^{[1
]}

Favia, Paola ^{[1
]}

Geypen, Jef ^{[1
]}

Bender, Hugo ^{[1
]}

Higuchi, Yuichi ^{[2
]}

Phatak, Anup ^{[3
]}

Thean, Aaron ^{[1
]}

Horiguchi, Naoto ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Assignee at IMEC from Panasonic, Kapeldreef 75, B-3001 Leuven, Belgium

[3] Assignee at IMEC from Applied Materials Belgium NV, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

Japanese Journal of Applied Physics | 2013年 / 52卷 / 4 PART 2期

关键词：

Bias temperature instability - Comprehensive evaluation - Gate resistance - High-k/metal gates - Intrinsic stress - Low threshold voltage - Materials selection - Technology nodes;

D O I：

04CA03

中图分类号：

学科分类号：

摘要：

引用

共 36 条

[1] W versus Co-Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes
Veloso, Anabela
Chew, Soon Aik
Schram, Tom
Dekkers, Harold
Van Ammel, Annemie
Witters, Thomas
Tielens, Hilde
Heylen, Nancy
Devriendt, Katia
Sebaai, Farid
Brus, Stephan
Ragnarsson, Lars-Ake
Pantisano, Luigi
Eneman, Geert
Carbonell, Laure
Richard, Olivier
Favia, Paola
Geypen, Jef
Bender, Hugo
Higuchi, Yuichi
Phatak, Anup
Thean, Aaron
Horiguchi, Naoto
JAPANESE JOURNAL OF APPLIED PHYSICS, 2013, 52 (04)
[2] Integration Challenges and Options of Replacement High-k/Metal Gate Technology for (Sub-)22nm Technology Nodes
Veloso, A.
Ragnarsson, L. -A.
Schram, T.
Chew, S. A.
Boccardi, G.
Thean, A.
Horiguchi, N.
CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2013 (CSTIC 2013), 2013, 52 (01): : 385 - 390
[3] Replacement Metal Gate/High-k Last Technology for Aggressively Scaled Planar and FinFET-based Devices
Veloso, A.
Lee, J. W.
Simoen, E.
Ragnarsson, L. -A.
Arimura, H.
Cho, M. J.
Boccardi, G.
Thean, A.
Horiguchi, N.
DIELECTRICS FOR NANOSYSTEMS 6: MATERIALS SCIENCE, PROCESSING, RELIABILITY, AND MANUFACTURING, 2014, 61 (02): : 225 - 235
[4] Application of Taguchi Method in Designing a 22nm High-k/Metal Gate NMOS Transistor
Maheran, Afifah A. H.
Menon, P. S.
Ahmad, I.
Shaari, S.
MICRO/NANO SCIENCE AND ENGINEERING, 2014, 925 : 514 - +
[5] Proposal of Single Metal/Dual High-k Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control
Mise, Nobuyuki
Morooka, Tetsu
Eimori, Takahisa
Ono, Tetsuo
Sato, Motoyuki
Kamiyama, Satoshi
Nara, Yasuo
Ohji, Yuzuru
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (01) : 85 - 92
[6] Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond
Choi, K.
Jagannathan, H.
Choi, C.
Edge, L.
Ando, T.
Frank, M.
Jamison, P.
Wang, M.
Cartier, E.
Zafar, S.
Bruley, J.
Kerber, A.
Linder, B.
Callegari, A.
Yang, Q.
Brown, S.
Stathis, J.
Iacoponi, J.
Paruchuri, V.
Narayanan, V.
2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : A138 - A139
[7] Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond
Choi, K.
Jagannathan, H.
Choi, C.
Edge, L.
Ando, T.
Frank, M.
Jamison, P.
Wang, M.
Cartier, E.
Zafar, S.
Bruley, J.
Kerber, A.
Linder, B.
Callegari, A.
Yang, Q.
Brown, S.
Stathis, J.
Iacoponi, J.
Paruchuri, V.
Narayanan, V.
2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2009, : 138 - +
[8] Plasma induced damage of aggressively scaled gate dielectric (EOT < 1.0nm) in metal gate/high-k dielectric CMOSFETs
Min, Kyung Seok
Kang, Chang Yong
Yoo, Ook Sang
Park, Byoung Jae
Kim, Sung Woo
Young, Chadwin D.
Heh, Dawei
Bersuker, Gennadi
Lee, Young Hun
Yeom, Geun Young
2008 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 46TH ANNUAL, 2008, : 723 - +
[9] Dual Channel FinFETs as a Single High-k/Metal Gate Solution Beyond 22nm Node
Smith, C. E.
Adhikari, H.
Lee, S-H.
Coss, B.
Parthasarathy, S.
Young, C.
Sassman, B.
Cruz, M.
Hobbs, C.
Majhi, P.
Kirsch, P. D.
Jammy, R.
2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 284 - +
[10] Intrinsic Dielectric Stack Reliability of a High Performance Bulk Planar 20nm Replacement Gate High-K Metal Gate Technology and Comparison to 28nm Gate First High-K Metal Gate Process
McMahon, W.
Tian, C.
Uppal, S.
Kothari, H.
Jin, M.
LaRosa, G.
Nigam, T.
Kerber, A.
Linder, B. P.
Cartier, E.
Lai, W. L.
Liu, Y.
Ramachandran, R.
Kwon, U.
Parameshwaran, B.
Krishnan, S.
Narayanan, V.
2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2013,

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