2.2.1 Test time reduction by optimal test sequencing1

被引:0
|
作者
Boumen, R. [1 ]
de Jong, I.S.M. [1 ]
van de Mortel-Fronczak, J.M. [1 ]
Rooda, J.E. [1 ]
机构
[1] Systems Engineering Group, Department of Mechanical Engineering, Eindhoven University of Technology, 5600 MB, Eindhoven, Netherlands
关键词
D O I
10.1002/j.2334-5837.2006.tb02741.x
中图分类号
学科分类号
摘要
引用
收藏
页码:259 / 269
相关论文
共 50 条
  • [1] TEST TIME REDUCTION THROUGH OPTIMAL DEGRADATION TESTING
    Yang, Guangbin
    INTERNATIONAL JOURNAL OF RELIABILITY QUALITY & SAFETY ENGINEERING, 2010, 17 (05): : 495 - 503
  • [2] Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction
    Chen, Linfeng
    Cui, Aijiao
    Chang, Chip-Hong
    IEEE TRANSACTIONS ON COMPUTERS, 2015, 64 (12) : 3417 - 3429
  • [3] Optimal and near-optimal test sequencing algorithms with realistic test models
    Raghavan, V
    Shakeri, M
    Pattipati, K
    IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS PART A-SYSTEMS AND HUMANS, 1999, 29 (01): : 11 - 26
  • [4] DECISION ANALYSIS FOR OPTIMAL TEST SEQUENCING
    BERGER, PD
    GERSTENF.A
    INDUSTRIAL ENGINEERING, 1972, 4 (07): : 20 - &
  • [5] DECISION ANALYSIS FOR OPTIMAL TEST SEQUENCING.
    Berger, P.D.
    Gerstenfeld, A.
    Industrial Engineering (Norcross, Georgia), 1972, 4 (07): : 20 - 25
  • [6] Test cost reduction for logic circuits: Reduction of test data volume and test application time
    Higami, Yoshinobu
    Kajihara, Seiji
    Ichihara, Hideyuki
    Takamatsu, Yuzo
    Systems and Computers in Japan, 2005, 36 (06): : 69 - 83
  • [7] Test time reduction methods for yield test structures
    Hess, CS
    Read, H
    Ren, J
    Weiland, LH
    Cheng, JJ
    Gan, C
    Karbasi, H
    Winters, S
    ICMTS 2003: PROCEEDINGS OF THE 2003 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2003, : 64 - 69
  • [8] Memory test time reduction by interconnecting test items
    Wu, WJ
    Tang, CY
    PROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000), 2000, : 290 - 298
  • [9] Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock
    Gunasekar, Sindhu
    Agrawal, Vishwani D.
    2014 IEEE 23RD NORTH ATLANTIC TEST WORKSHOP (NATW), 2014, : 52 - 56
  • [10] Test time reduction for IDDQ testing by arranging test vectors
    Yotsuyanagi, H
    Hashizume, M
    Tamesada, T
    PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS 02), 2002, : 423 - 428