GraphAGILE: An FPGA-based Overlay Accelerator for Low-latency GNN Inference

被引：0

作者：

Zhang, Bingyi ^{[1
]}

Zeng, Hanqing ^{[1
]}

Prasanna, Viktor ^{[1
]}

机构：

[1] The Department of Electrical and Computer Engineering, University of Southern California, Los Angeles,CA,90089, United States

来源：

arXiv | 2023年

关键词：

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Convolutional codes - Dynamic loads - Integrated circuit design - Matrix algebra - Memory architecture - Network architecture - Neural network models - Program compilers

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