Clock-gating approach to low power domino circuit synthesis

被引：0
|
作者：
机构：
[1] Kadiyala, Sai P.
[2] Samanta, Debasis
来源：
| 1600年 / Acta Press卷 / 36期
关键词：
19;
D O I：
10.2316/Journal.202.2014.4.202-3938
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [21] Exercising Symbolic Discrete Control for Designing Low-power Hardware Circuits: an Application to Clock-gating
    Ozbaltan, Mete
    Berthier, Nicolas
    IFAC PAPERSONLINE, 2018, 51 (07): : 120 - 126
  • [22] PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files
    Namazi, Alireza
    Abdollahi, Meisam
    2017 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2017, : 323 - 328
  • [23] System Level Simulation Guided Approach to Improve the Efficacy of Clock-gating
    Ahuja, Sumit
    Zhang, Wei
    Shukla, Sandeep K.
    2010 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT), 2010, : 9 - 16
  • [24] Impact of Clock-Gating on Power Distribution Network using Wavelet Analysis
    Patil, Vinay C.
    Srinivasan, Sudarshan
    Burleson, Wayne P.
    Kundu, Sandip
    2013 26TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2013 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2013, : 80 - 85
  • [25] Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating
    Lingasubramanian, Karthikeyan
    Calimera, Andrea
    Macii, Alberto
    Macii, Enrico
    Poncino, Massimo
    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION, AND SIMULATION, 2011, 6951 : 214 - 225
  • [26] Clock-gating in FPGAs:: A novel and comparative evaluation
    Zhang, Yan
    Roivainen, Jussi
    Mammela, Aarne
    DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2006, : 584 - +
  • [27] Improved clock-gating through transparent pipelining
    Jacobson, HM
    ISLPED '04: PROCEEDINGS OF THE 2004 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2004, : 26 - 31
  • [28] O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
    Rahman, M. Sazadur
    Guo, Rui
    Kamali, Hadi M.
    Rahman, Fahim
    Farahmandi, Farimah
    Abdel-Moneum, Mohamed
    Tehranipoor, Mark
    PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022, 2022, : 775 - 780
  • [29] Low power sequential circuit design by using priority encoding and clock gating
    Wu, XW
    Pedram, M
    ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, : 143 - 148
  • [30] Improved Clock-Gating Control Scheme for Transparent Pipeline
    Choi, Jung Hwan
    Kim, Byung Guk
    Dasgupta, Aurobindo
    Roy, Kaushik
    2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 396 - +
12345