Clock-gating approach to low power domino circuit synthesis

被引：0
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机构：
[1] Kadiyala, Sai P.
[2] Samanta, Debasis
来源：
| 1600年 / Acta Press卷 / 36期
关键词：
19;
D O I：
10.2316/Journal.202.2014.4.202-3938
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