共 50 条
- [21] Equivalence checking of combinational circuits using Boolean expression diagrams IEEE Trans Comput Aided Des Integr Circuits Syst, 7 (903-917):
- [24] Non-miter-based combinational equivalence checking by comparing BDDs with different variable orders FORMAL METHODS IN COMPUTER-AIDED DESIGN, 2004, 3312 : 144 - 158
- [26] Non-miter-based combinational equivalence checking by comparing BDDs with different variable orders FORMAL METHODS IN COMPUTER-AIDED DESIGN, PROCEEDINGS, 2004, 3312 : 144 - 158
- [27] Combinational equivalence checking using Boolean Satisfiability and Binary Decision Diagrams DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 122 - 126
- [28] Equivalence Checking Paradigms in Quantum Circuit Design PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022, 2022, : 517 - 522
- [29] Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 175 - 180
- [30] Iterated calculation of global implications and recursive learning in combinational equivalence checking PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 2000, : 976 - 979