Low-power ternary inverter using vertical tunnel field-effect transistor with pocket

This paper proposes a vertical tunnel FET with pocket (VP-TFET)-based standard ternary inverter (T-inverter) model for low-power applications. Using TCAD Sentaurus tool and mixed-mode simulations, it is verified that the device can exhibit T-inverter voltage transfer characteristics (VTCs) with three steady output voltage levels when the doping length and concentration of the pocket are optimized The device's T-inverter characteristics are achieved by employing channel-channel and source-channel tunnelling mechanisms. Current matching is crucial for n-/p-type devices to produce a steady third output voltage state. The proposed ternary inverter's static noise margin (SNM) and static and dynamic power dissipations are computed to be 220 mV, 4.8 x 10-12 W, and 4 x 10-12 W, respectively, which assures better noise immunity and low power consumption compared to other models.