SHA-256 Hardware Proposal for IoT Devices in the Blockchain Context

被引:2
|
作者
Santos Jr, Carlos E. B. [1 ,2 ]
da Silva, Lucileide M. D. [1 ,2 ,3 ]
Torquato, Matheus F. [1 ]
Silva, Sergio N. [1 ,2 ]
Fernandes, Marcelo A. C. [1 ,2 ,4 ]
机构
[1] Fed Univ Rio Grande Norte UFRN, InovAI Lab, nPITI IMD, BR-59078970 Natal, Brazil
[2] Univ Fed Rio Grande do Norte, nPITI IMD, Leading Adv Technol Ctr Excellence LANCE, BR-59078970 Natal, Brazil
[3] Fed Inst Educ Sci & Technol Rio Grande Norte, BR-59200000 Santa Cruz, Brazil
[4] Univ Fed Rio Grande do Norte, Dept Comp Engn & Automat, BR-59078970 Natal, Brazil
关键词
FPGA; IoT; blockchain; SHA-256; hardware; PARALLEL IMPLEMENTATION; ALGORITHM; FPGA; ARCHITECTURE; SECURE; PROCESSOR;
D O I
10.3390/s24123908
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
This work proposes an implementation of the SHA-256, the most common blockchain hash algorithm, on a field-programmable gate array (FPGA) to improve processing capacity and power saving in Internet of Things (IoT) devices to solve security and privacy issues. This implementation presents a different approach than other papers in the literature, using clustered cores executing the SHA-256 algorithm in parallel. Details about the proposed architecture and an analysis of the resources used by the FPGA are presented. The implementation achieved a throughput of approximately 1.4 Gbps for 16 cores on a single FPGA. Furthermore, it saved dynamic power, using almost 1000 times less compared to previous works in the literature, making this proposal suitable for practical problems for IoT devices in blockchain environments. The target FPGA used was the Xilinx Virtex 6 xc6vlx240t-1ff1156.
引用
收藏
页数:25
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